1. Field of the Invention
The present invention relates to a semiconductor device in which a MOS transistor is formed on a semiconductor film on an insulating film and, more particularly, to a semiconductor device in which a MOS transistor constituting a sensor amplifier or a boosting circuit of a DRAM is improved.
2. Description of the Related Art
High performance of a recent semiconductor integrated circuit in, especially, a silicon MOS transistor technique is considerably developed. In this silicon MOS transistor technique, it is known that a micropatterned, high-speed, and high-performance element can be realized by forming a MOS transistor on an SOI (Silicon-On-Insulator) film (to be referred to as an SOI-MOSFET hereinafter).
FIG. 1 is a plan view showing a layout pattern of a conventional sense amplifier using such an SOI-MOSFET, and FIGS. 2A and 2B are sectional views showing the conventional sense amplifiers along lines 2Axe2x80x942A and 2Bxe2x80x942B in FIG. 1, respectively.
FIG. 1 shows a sense amplifier SA, a bit line BL, a control line 1 for connecting a common source terminal of the sense amplifier SA, a source-contact portion 2, a drain-contact portion 3, and a gate-contact portion 4.
FIGS. 2A and 2B show a p-type monocrystal silicon film 7 as an SOI film. A silicon oxide film (SiO2 film) 6 is formed on the bottom and side surfaces of the p-type monocrystal silicon film 7. The silicon oxide film 6 on the bottom surface is an insulating film of an SOI substrate, and the silicon oxide film 6 on each side surface is an element isolation insulation film.
An n-type source region 8 and an n-type drain region 9 are selectively formed in the p-type monocrystal silicon film 7. A gate electrode 11 is arranged on the p-type monocrystal silicon film 7 in a channel region between the n-type source region 8 and the n-type drain region 9 through a gate oxide film 10.
In the SOI-MOSFET, due to a so-called substrate floating effect, problems such as a low drain breakdown voltage or an unstable drain current in a switching operation are posed.
In particular, in a flip-flop type sense amplifier used in a DRAM or the like or a current mirror type differential amplifier, when an n-type SOI-MCSFET is used in a potential difference detection unit, holes are stored in an SOI-MOSFET channel portion, and the threshold value of the SOI-MOSFET decreases. Since the decrease in threshold value depends on the number of stored holes, the decrease in threshold value depends on a transistor. For this reason, the threshold value is unbalanced, and detection sensitivity to a potential difference. When the decrease in threshold value is considerably large, an erroneous operation may be caused.
In a pump circuit constituting a boosting circuit or a lowering circuit, when a capacitor constituting a pump has first and second electrodes, and an SOI-MOSFET is used as a switching means for connecting the first electrode of the capacitor to an output, a decrease in drain breakdown voltage is caused by the substrate floating effect of the SOI-MOSFET.
For example, in the lowering circuit, when the first potential is boosted at a timing at which the potential of the second electrode is charged by a capacitor driver circuit, the SOI-MOSFET must be turned off. When an n-type SOI-MOSFET is used the above SOI-MOSFET, the potential of the first electrode serving as a drain is boosted, the capacity coupling between the drain and the substrate portion of the SOI-MOSFET boosts the potential of this substrate portion, and the cut-off characteristics of the SOI-MOSFET are degraded. In the worst case, drain breakdown is caused. In addition, holes generated by slight drain breakdown are stored for a reason except for the above capacity coupling, and drain breakdown is caused by the substrate floating effect.
Furthermore, although an accurate reference voltage generation circuit is required to use the reference voltage as a reference for checking whether an input signal is set to be xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d in a DRAM or the like, a bulk type pn diode used in a conventional DRAM or the like cannot be used in the SOI-MOSFET without increasing the number of steps (costs). Therefore, means for generating a stable reference potential without largely increasing the number of steps is desired.
As described above, since no contact with the substrate can be obtained in the semiconductor device using the conventional SOI-MOSFET, a substrate floating effect is disadvantageously caused. In particular, in sense amplifiers for amplifying a fine potential read out on a bit line pair, since the substrate potentials of two transistors constituting a pair of sense amplifiers are set in a floating state, the threshold values of the transistors are difference from each other, and an accurate sensing operation cannot be performed (subject matter 1). In addition to realization of the accurate sensing operation, high-density integration (subject matter 2), moderation of design rules (subject matter 3), and a countermeasure against noise (subject matter 4) must be realized.
Furthermore, in a pump circuit constituting a boosting circuit or a lowering circuit, the cut-off characteristics of an SOI-MOSFET are degraded, and drain breakdown is caused in the worst case (subject matter 5). In the SOI-MOSFET, a stable reference potential cannot be generated without largely increasing the number of steps (subject matter 6).
It is an object of the present invention to provide a semiconductor device which can prevent a substrate floating effect of an SOI-MOSFET to realize a highly reliable sense amplifier or the like and realizes high-density integration, moderation of design rules, and a reduction in noise.
Means for solving subject matter 1 is as follows. That is, a diffusion layer region of the same conductivity type as that of a substrate is formed in a common source region, or a portion of each drain region in a sense amplifier formed by an SOI-MOSFET to connect the substrates of a pair of transistors to each other, thereby making the potentials of the substrates equal to each other (arrangement 1-1). In order to make the above means further effective, a contact is formed in the common diffusion layer region to connect the common diffusion layer region to a power supply line or a signal line (arrangement 1-2).
According to arrangement 1 of the present invention, in a sense amplifier constituted by an SOI-MOSFET which detects and amplifies a micro-potential difference, the substrate potentials of a pair of transistors are equal to each other. For this reason, the threshold values of the transistors change in the same manner, and a potential difference can be accurately detected. For this reason, an erroneous sensing operation can be prevented.
In addition, since the contact with a substrate is formed, the substrate potentials are not set in a floating state, and problems such as storage of holes in a channel portion and a decrease in drain breakdown voltage are solved. Therefore, a highly reliable DRAM can be realized.
Means for solving subject matter 2 is that the substrate contact and a source contact are used common (arrangement 2-1), or that a p-type region is common to upper and lower (in a word line direction) sense amplifiers (arrangement 2-2).
According to arrangement 2, the substrate contact and the source contact are used common, a contact-contact interval is not required, and high-density integration can be obtained. When p-type regions are connected to each other in a word line direction, an implant-implant interval is not required, and high-density integration can be obtained. In addition, when p-type regions are connected to each other in a word line direction, the substrate potentials and threshold values of the sense amplifiers on pair of adjacent bits can be made equal to each other, and sensing operations can be started at the same timing. For this reason, a sense amplifier is not erroneously operated in reception of noise from an adjacent column.
Means for solving subject matter 3 employs an arrangement in which sense amplifiers are shifted from each other in a bit line direction (arrangement 3-1), an arrangement using a layout in which a through bit line is arranged and one sense amplifier is arranged every four bit lines (arrangement 3-2), or an arrangement in which a gate is vertically arranged (arrangement 3-3). When two p-type regions are formed in both the ends a gate polysilicon portion (arrangement 3-4), a layout strong to a shift in mask alignment of an implant can be obtained.
According to arrangement 3 of the present invention, when the sense amplifiers are shifted from each other in the bit line direction (lateral direction), and a layout in which one sense amplifier is arranged every four bit lines, design rules in the vertical direction can be moderated. When the gate polysilicon portion of a transistor is vertically arranged, a gate length L of the transistor can be increased, and variations in threshold value can be decreased. In addition, when two p-type regions are formed in both the ends of a gate polysilicon, a layout strong to a shift in mask alignment of an implant can be obtained.
Means for solving subject matter 4 is that bit lines cross each other (arrangement 4).
According to arrangement 4 of the present invention, when a pair of bit lines cross each other, noise generated by adjacent bit lines can be eliminated.
In addition to arrangements 1 to 4 described above, various combinations such as arrangements 1-1 and 2-2, arrangements 1-1 and 3-2, arrangements 1-1 and 2-2, arrangements 3-4 and, . . . , can be used. Therefore, the effects of these arrangements can be added to each other.
A means for solving subject matter 5 employs an arrangement in which an n-type (in case of a boosting circuit) or p-type (in case of a lowering circuit) SOI-MOSFET is used, the gate length of the SOI-MOSFET is set to be larger than the minimum gate length of an SOI-MOSFET constituting a circuit except for the boosting circuit or the lowering circuit, a semiconductor having a bandgap width smaller than a channel portion is formed in at least a portion of the source/drain region of the SOI-MOSFET constituting the boosting circuit or lowering circuit (arrangement 5).
Arrangement 5 comprises a pn diode using a junction between a p-type diffusion layer formed simultaneously with a portion of the source region of the SOI-MOSFET and consisting of the same material as that of the source region and a first n-type diffusion layer, and a pn diode using a junction between a p-type semiconductor having a bandgap width equal to that of the channel portion and the first n-type semiconductor. The difference between the threshold values of the two pn junction diodes is used as a reference potential.
According to arrangement 5 of the present invention, with respect to a boosting circuit, a capacitor performs discharge from the second electrode of the capacitor, and the potential of the first electrode is lowered, in the n-type SOI-MOSFET (M1) in which the first electrode and the output are connected to each other, the potential of the substrate portion of the SOI-MOSFET is lowered by capacity coupling between the substrate portion and the first electrode. For this reason, the cut-off characteristics change to be improved, and trigger which causes drain breakdown can be advantageously avoided. When the potential of the first electrode is lower than an output voltage, holes generated for some reasons such as slight drain breakdown are absorbed in a narrow bandgap semiconductor portion to suppress a substrate floating effect, thereby preventing drain breakdown. In addition, when the gate length of the SOI-MOSFET is increased, an electric field to be applied is moderated, and a drain breakdown voltage can be increased.
In a means for solving subject matter 6, the bandgap width of at least a portion of the source region of the SOI-MOSFET is smaller than that of the channel region, a first pn diode using a junction between a p-type diffusion layer formed simultaneously with a portion of the source region of the SOI-MOSFET and consisting of the same material as that of the source region and a first n-type diffusion layer, and a second pn diode using a junction between a p-type semiconductor having a bandgap width equal to that of the channel portion and the first n-type semiconductor are arranged (arrangement 6).
In arrangement 6, the SOI-MOSFET is an n-type SOI-MOSFET, and at least a pair of n-type SOI-MOSFETs are arranged on the semiconductor integrated circuit. The pair of n-type SOI-MOSFETs have gates which respectively receive potentials 1 and 2, and a circuit for discriminating the magnitudes of the potentials 1 and 2 on the basis of the difference between the conductances of the pair of n-type SOI-MOSFETs is constituted, and the channel regions of the pair of SOI-MOSFETs are connected to each other by an impurity diffusion layer of the same conductivity type as that of the channel region described above.
According to arrangement 6 of the present invention, a semiconductor having a bandgap width smaller than that of the channel portion is used as a portion of the source region of the n-type SOI-MOSFET, and the pn diode using the junction between the p-type diffusion layer formed simultaneously with the portion of the source region of the SOI-MOSFET and consisting of the same material as that of the source region and the first n-type diffusion layer, and the pn diode using the junction between the p-type semiconductor having a bandgap width equal to that of the channel portion and the first n-type semiconductor are arranged. When the difference between the threshold values of these diodes is used as a reference potential, this reference potential is not easily changed by a change in temperature.
As described above, according to the present invention, in a sense amplifier constituted by SOI-MOSFETs, the substrate potentials of the SOI-MOSFETs can be made equal to each other, or the SOI-MOSFETs can be connected to a control line. For this reason, a substrate floating effect can be prevented, and an erroneous operation or the like caused by a change in threshold value can be prevented. In addition, high-density integration can be obtained with moderating design rules. Therefore, a high-density semiconductor device which has high reliability and effectively uses the advantages of the SOI-MOSFET can be realized.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the present invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the present invention in which:
FIG. 1 is a plan view showing a layout pattern of conventional sense amplifiers;
FIGS. 2A and 2B are sectional view showing the conventional sense amplifier along lines 2Axe2x80x942A and 2Bxe2x80x942B in FIG. 1, respectively;
FIG. 3 is a circuit diagram showing the arrangement of a sense amplifier using an SOI-MOSFET according to the first embodiment;
FIG. 4 is a plan view showing a layout pattern of the sense amplifier according to the first embodiment;
FIG. 5 is a sectional view showing the element structure of the SOI-MOSFET according to the first embodiment;
FIG. 6 is a plan view showing another layout pattern of the sense amplifier according to the first embodiment;
FIGS. 7A and 7B are sectional views showing the sense amplifier along lines 7Axe2x80x947A and 7Bxe2x80x947B in FIG. 6, respectively;
FIG. 8A is a circuit diagram showing the arrangement of a current mirror type sense amplifier, and FIG. 8B is a plan view showing the layout of the current mirror type sense amplifier in FIG. 8A;
FIG. 9 is a circuit diagram showing the arrangement of a modification of the current mirror type sense amplifier in FIG. 8A;
FIG. 10 is a circuit diagram showing the arrangement of a sense amplifier of a DRAM according to the second embodiment;
FIG. 11 is a plan view showing a layout pattern of the sense amplifiers according to the second embodiment;
FIGS. 12A and 12B are sectional views showing the sense amplifier along lines 12Axe2x80x9412A and 12Bxe2x80x9412B in FIG. 11;
FIG. 13 is a plan view showing another layout pattern of the sense amplifiers according to the second embodiment;
FIG. 14 is a plan view showing a layout pattern of sense amplifiers according to the third embodiment;
FIG. 15 is a plan view showing another layout pattern of the sense amplifiers according to the third embodiment;
FIG. 16 is a plan view showing a layout pattern of sense amplifiers according to the fourth embodiment;
FIG. 17 is a plan view showing another layout pattern of the sense amplifiers according to the fourth embodiment;
FIG. 18 is a plan view showing a layout pattern of sense amplifiers according to the fifth embodiment;
FIG. 19 is a plan view showing another layout pattern of the sense amplifiers according to the fifth embodiment;
FIG. 20 is a plan view showing a layout pattern of sense amplifiers according to the sixth embodiment;
FIG. 21 is a plan view showing another layout pattern of the sense amplifiers according to the sixth embodiment;
FIG. 22 is a plan view showing a layout pattern of sense amplifiers according to the seventh embodiment;
FIG. 23 is a plan view showing another layout pattern of the sense amplifiers according to the seventh embodiment;
FIG. 24 is a plan view showing a layout pattern of sense amplifiers according to the eighth embodiment;
FIG. 25 is a plan view showing another layout pattern of the sense amplifiers according to the eighth embodiment;
FIG. 26 is a plan view showing a layout pattern of sense amplifiers according to the ninth embodiment;
FIG. 27 is a plan view showing another layout pattern of the sense amplifiers according to the ninth embodiment;
FIG. 28 is a plan view showing a layout pattern of sense amplifiers according to the 10th embodiment;
FIG. 29 is a plan view showing another layout pattern of the sense amplifiers according to the 10th embodiment;
FIG. 30 is a plan view showing a layout pattern of sense amplifiers according to the 11th embodiment;
FIG. 31 is a plan view showing another layout pattern of the sense amplifiers according to the 11th embodiment;
FIG. 32 is a plan view showing a layout pattern of sense amplifiers according to the 12th embodiment;
FIG. 33 is a plan view showing another layout pattern of the sense amplifiers according to the 12th embodiment;
FIG. 34 is a plan view showing a layout pattern of sense amplifiers according to the 13th embodiment;
FIG. 35 is a plan view showing another layout pattern of the sense amplifiers according to the 13th embodiment;
FIG. 36 is a plan view showing a layout pattern of sense amplifiers according to the 14th embodiment;
FIG. 37 is a plan view showing another layout pattern of the sense amplifiers according to the 14th embodiment;
FIG. 38 is a plan view showing a layout pattern of sense amplifiers according to the 15th embodiment;
FIG. 39 is a plan view showing another layout pattern of the sense amplifiers according to the 15th embodiment;
FIG. 40 is a plan view showing a layout pattern of sense amplifiers according to the 16th embodiment;
FIG. 41 is a plan view showing another layout pattern of the sense amplifiers according to the 16th embodiment;
FIG. 42 is a plan view showing a layout pattern of sense amplifiers according to the 17th embodiment;
FIG. 43 is a plan view showing another layout pattern of the sense amplifiers according to the 17th embodiment;
FIG. 44 is a plan view showing a layout pattern of sense amplifiers according to the 18th embodiment;
FIG. 45 is a plan view showing another layout pattern of the sense amplifiers according to the 18th embodiment;
FIG. 46 is a plan view showing a layout pattern of sense amplifiers according to the 19th embodiment;
FIG. 47 is a plan view showing another layout pattern of the sense amplifiers according to the 19th embodiment;
FIG. 48 is a plan view showing a layout pattern of sense amplifiers according to the 20th embodiment;
FIG. 49 is a plan view showing another layout pattern of the sense amplifiers according to the 20th embodiment;
FIG. 50 is a plan view showing a layout pattern of sense amplifiers according to the 21st embodiment;
FIG. 51 is a plan view showing another layout pattern of the sense amplifiers according to the 21st embodiment;
FIG. 52 is a plan view showing a layout pattern of sense amplifiers according to the 22nd embodiment;
FIG. 53 is a plan view showing another layout pattern of the sense amplifiers according to the 22nd embodiment;
FIG. 54 is a plan view showing a layout pattern of sense amplifiers according to the 23rd embodiment;
FIG. 55 is a plan view showing another layout pattern of the sense amplifiers according to the 23rd embodiment;
FIG. 56 is a plan view showing a layout pattern of sense amplifiers according to the 24th embodiment;
FIG. 57 is a plan view showing another layout pattern of the sense amplifiers according to the 24th embodiment;
FIG. 58 is a plan view showing a layout pattern of sense amplifiers according to the 25th embodiment;
FIG. 59 is a plan view showing another layout pattern of the sense amplifiers according to the 25th embodiment;
FIG. 60 is a plan view showing a layout pattern of sense amplifiers according to the 26th embodiment;
FIG. 61 is a plan view showing another layout pattern of the sense amplifiers according to the 26th embodiment;
FIG. 62 is a plan view showing a layout pattern of sense amplifiers according to the 27th embodiment;
FIG. 63 is a plan view showing another layout pattern of the sense amplifiers according to the 27th embodiment;
FIG. 64 is a plan view showing a layout pattern of sense amplifiers according to the 28th embodiment;
FIG. 65 is a plan view showing another layout pattern of the sense amplifiers according to the 28th embodiment;
FIG. 66 is a plan view showing a layout pattern of sense amplifiers according to the 29th embodiment;
FIG. 67 is a plan view showing another layout pattern of the sense amplifiers according to the 29th embodiment;
FIG. 68 is a plan view showing a layout pattern of sense amplifiers according to the 30th embodiment;
FIG. 69 is a plan view showing another layout pattern of the sense amplifiers according to the 30th embodiment;
FIG. 70 is a plan view showing a layout pattern of sense amplifiers according to the 31st embodiment;
FIG. 71 is a plan view showing another layout pattern of the sense amplifiers according to the 31st embodiment;
FIG. 72 is a plan view showing a layout pattern of sense amplifiers according to the 32nd embodiment;
FIG. 73 is a plan view showing another layout pattern of the sense amplifiers according to the 32nd embodiment;
FIG. 74 is a plan view showing a layout pattern of sense amplifiers according to the 33rd embodiment;
FIG. 75 is a plan view showing another layout pattern of the sense amplifiers according to the 33rd embodiment;
FIG. 76 is a plan view showing a layout pattern of sense amplifiers according to the 34th embodiment;
FIG. 77 is a plan view showing another layout pattern of the sense amplifiers according to the 34th embodiment;
FIG. 78 is a plan view showing a layout pattern of sense amplifiers according to the 35th embodiment;
FIG. 79 is a plan view showing another layout pattern of the sense amplifiers according to the 35th embodiment;
FIG. 80 is a plan view showing a layout pattern of sense amplifiers according to the 36th embodiment;
FIG. 81 is a plan view showing another layout pattern of the sense amplifiers according to the 36th embodiment;
FIG. 82 is a plan view showing a layout pattern of sense amplifiers according to the 37th embodiment;
FIG. 83 is a plan view showing another layout pattern of the sense amplifiers according to the 37th embodiment;
FIG. 84 is a plan view showing a layout pattern of sense amplifiers according to the 38th embodiment;
FIG. 85 is a plan view showing another layout pattern of the sense amplifiers according to the 38th embodiment;
FIG. 86 is a plan view showing a layout pattern of sense amplifiers according to the 39th embodiment;
FIG. 87 is a plan view showing another layout pattern of the sense amplifiers according to the 39th embodiment;
FIG. 88 is a plan view showing a layout pattern of sense amplifiers according to the 40th embodiment;
FIG. 89 is a plan view showing another layout pattern of the sense amplifiers according to the 40th embodiment;
FIG. 90 is a plan view showing a layout pattern of sense amplifiers according to the 41st embodiment;
FIG. 91 is a plan view showing another layout pattern of the sense amplifiers according to the 41st embodiment;
FIG. 92 is a plan view showing a layout pattern of sense amplifiers according to the 42nd embodiment;
FIG. 93 is a plan view showing another layout pattern of the sense amplifiers according to the 42nd embodiment;
FIG. 94 is a plan view showing a layout pattern of sense amplifiers according to the 43rd embodiment;
FIG. 95 is a plan view showing another layout pattern of the sense amplifiers according to the 43rd embodiment;
FIG. 96 is a circuit diagram showing the arrangement of sense amplifiers according to the 44th embodiment;
FIG. 97 is a plan view showing a layout pattern of the sense amplifiers according to the 44th embodiment;
FIG. 98 is a plan view showing a layout pattern of sense amplifiers according to the 45th embodiment;
FIG. 99 is a plan view showing a layout pattern of sense amplifiers according to the 46th embodiment;
FIG. 100 is a plan view showing a layout pattern of sense amplifiers according to the 47th embodiment;
FIG. 101 is a plan view showing a layout pattern of sense amplifiers according to the 48th embodiment;
FIG. 102 is a plan view showing a layout pattern of sense amplifiers according to the 49th embodiment;
FIG. 103 is a plan view showing a layout pattern of sense amplifiers according to the 50th embodiment;
FIG. 104 is a plan view showing a layout pattern of sense amplifiers according to the 51st embodiment;
FIG. 105 is a plan view showing a layout pattern of sense amplifiers according to the 52nd embodiment;
FIG. 106 is a plan view showing a layout pattern of the sense amplifiers according to the 52nd embodiment;
FIG. 107 is a plan view showing a layout pattern of sense amplifiers according to the 53rd embodiment;
FIG. 108 is a plan view showing a layout pattern of sense amplifiers according to the 54th embodiment;
FIG. 109 is a plan view showing a layout pattern of sense amplifiers according to the 55th embodiment;
FIG. 110 is a plan view showing a layout pattern of sense amplifiers according to the 56th embodiment;
FIG. 111 is a plan view showing a layout pattern of sense amplifiers according to the 57th embodiment;
FIG. 112 is a plan view showing a layout pattern of sense amplifiers according to the 58th embodiment;
FIG. 113 is a plan view showing a layout pattern of sense amplifiers according to the 59th embodiment;
FIG. 114 is a plan view showing a layout pattern of sense amplifiers according to the 60th embodiment;
FIG. 115 is a plan view showing a layout pattern of sense amplifiers according to the 61st embodiment;
FIG. 116 is a plan view showing a layout pattern of sense amplifiers according to the 62nd embodiment;
FIG. 117 is a plan view showing a layout pattern of sense amplifiers according to the 63rd embodiment;
FIG. 118 is a plan view showing a layout pattern of sense amplifiers according to the 64th embodiment;
FIG. 119 is a plan view showing a layout pattern of sense amplifiers according to the 65th embodiment;
FIG. 120 is a plan view showing a layout pattern of sense amplifiers according to the 66th embodiment;
FIG. 121 is a plan view showing a layout pattern of sense amplifiers according to the 67th embodiment;
FIG. 122 is a plan view showing a layout pattern of sense amplifiers according to the 68th embodiment;
FIG. 123 is a plan view showing a layout pattern of sense amplifiers according to the 69th embodiment;
FIG. 124 is a plan view showing a layout pattern of sense amplifiers according to the 70th embodiment;
FIG. 125 is a plan view showing a layout pattern of sense amplifiers according to the 71st embodiment;
FIG. 126 is a plan view showing a layout pattern of sense amplifiers according to the 72nd embodiment;
FIG. 127 is a plan view showing a layout pattern of sense amplifiers according to the 73rd embodiment;
FIG. 128 is a plan view showing a layout pattern of sense amplifiers according to the 74th embodiment;
FIG. 129 is a plan view showing a layout pattern of sense amplifiers according to the 75th embodiment;
FIG. 130 is a plan view showing a layout pattern of sense amplifiers according to the 76th embodiment;
FIG. 131 is a plan view showing a layout pattern of sense amplifiers according to the 77th embodiment;
FIG. 132 is a plan view showing a layout pattern of sense amplifiers according to the 78th embodiment;
FIG. 133 is a plan view showing a layout pattern of sense amplifiers according to the 79th embodiment;
FIG. 134 is a plan view showing a layout pattern of sense amplifiers according to the 80th embodiment;
FIG. 135 is a plan view showing a layout pattern of sense amplifiers according to the 81st embodiment;
FIG. 136 is a plan view showing a layout pattern of sense amplifiers according to the 82nd embodiment;
FIG. 137 is a plan view showing a layout pattern of sense amplifiers according to the 83rd embodiment;
FIG. 138 is a plan view showing a layout pattern of sense amplifiers according to the 84th embodiment;
FIG. 139 is a plan view showing a layout pattern of sense amplifiers according to the 85th embodiment;
FIG. 140 is a plan view showing a layout pattern of sense amplifiers according to the 86th embodiment;
FIG. 141 is a plan view showing a layout pattern of sense amplifiers according to the 87th embodiment;
FIG. 142 is a plan view showing another layout pattern of the sense amplifiers according to the 87th embodiment;
FIG. 143A is a circuit diagram showing the arrangement of a boosting circuit using an SOI-MOSFET according to the 88th embodiment, and FIG. 143B is a timing chart of the boosting circuit in FIG. 143A;
FIG. 144 is a sectional view showing the SOI-MOSFET in the 88th embodiment;
FIGS. 145A and 145B are sectional views showing the element structure of the SOI-MOSFET in the 88th embodiment;
FIG. 146A is a sectional view showing a diode formed by a pn junction according to the 89th embodiment, and FIG. 146B and 146C are equivalent circuits of the diode in FIG. 146A; and
FIG. 147 is a circuit diagram showing the arrangement of a circuit using the diode in FIG. 146A.